1. Field of the Invention
This invention relates to clock signals in communication networks, and, more particularly, to clock signal decoupling for clock signal alignment for synchronous operation.
2. Description of the Related Art
To accommodate increasing demand for bandwidth, optical networking has become more prevalent. Two well-known types of optical networks are Synchronous Optical Network (SONET) and Synchronous Digital Hierarchy (SDH). Sometimes such networks are referred to as broadband networks, namely, networks capable of supporting interactive multimedia applications, as mentioned in “SONET” (Second Edition) by Walter J. Goralski (“Goralski”), at pages 20–23. As SONET and SDH have similar frame overhead configurations, for purposes of clarity, the remainder of this specification will tend to be disclosed in more terms of a synchronous optical network using SDH than SONET. However, it will be appreciated by those of skill in the art, that this specification is equally applicable to other types of synchronous optical networks, including but not limited to SONET.
A key feature of SDH networks is synchronous operation. SDH networks are synchronized to a much higher degree than prior T-carrier trunking networks, so much so that such prior synchronized networks are referred to as part of a pleisochronous digital hierarchy (PDH).
In an SDH network, bits are sent from one node to another. These bits may be received or passed through such a node. Particularly, when bits are taken off one link and put on another link as for pass through bits such as occurs in an add/drop multiplexer (ADM) or a digital cross-connect system (DCS), the relationship between frames in a synchronous multiplexing scheme, such as SDH, becomes important. In other words, a bit that is dropped from one link must occupy the same bit position within a byte in a frame structure when added to another link. Thus, a receive clock on an input port of a node must agree within a significant amount of precision with a transmit clock on an output port of the node. An SDH network, having links where bits are terminated in endpoint devices at each end, has a distributed network-timing signal, such as from a stratum clock via global positioning satellite. This distributed network-timing signal is distributed to separate nodes on the network. However, jitter and other variations in clocking still occur.
FIG. 1 is a block diagram of an exemplary portion of an embodiment of a portion of a receive side interface of a network node or network element 10 of the prior art. Synchronous Transport Module-level N (STM-N), for N equal to 1, 4, 16, 64, etc., signals 11-1 to 11-N are line inputs to respective clock recovery units (CRUs) 19-1 to 19-N. For SDH, data rate for an STM-N signal is N times 155.52 mega-bits per second (Mbps).
CRUs 19-1 to 19-N provide STM-N* signals 11-1* to 11-N* and receive (Rx) line clock (Clk) signals 12-1 to 12-N as outputs as illustratively shown to respective line interfaces 18-1 to 18-N. STM-N* signal 11-N* is equivalent to STM-N signal 11-N without clock pulses, and CRU 19-N provides a recovered Rx line clock 12-N.
Each line interface 18-1 to 18-N comprises a serial-in parallel-out (SIPO) register 23, a framer 21 and a frame timing generator 22. Line interfaces 18-1 to 18-N are used to convert STM-N* signals 11-1* to 11-N* serial input to parallel data output signals 25-1 to 25-N and to convert Rx line clock signals 12-1 to 12-N to Rx parallel clock signals (RxParClk) 24-1 to 24-N. Rx parallel clock signals 24-1 to 24-N are produced by dividing Rx line clock signals 12-1 to 12-N by a number corresponding to bit width of of parallel data output signals 25-1 through 25-N. For example, if data output signal 25-N is 8 bits wide, then Rx line clock signal is divided by eight to provide Rx parallel clock signal 24-N. An N-by-1 array 16 of pointer processors 15-1 to 15-N respectively receive signals 24-1 to 24-N and 25-1 to 25-N to provide respective pointer outputs 14-1 to 14-N. Each pointer processor 15-1 to 15-N has a first-in, first-out (FIFO) buffer 17-1 to 17-N.
Array 16 represents a multi-channel physical layer device, where physical layer indicates where line input, such as fiber optic line signals, meets integrated circuit. FIG. 1 is a channelized approach to dealing with such asynchronicity. In other words, each pointer output signal 14-1 to 14-N is provided separately or on a per channel basis. This is in contrast, for example, to receiving line input to a byte-interleaved multiplexer (MUX) and providing a single output with bytes interleaved from a plurality of line inputs.
Pointer processors 15-1 to 15-N, and more particularly buffers 17-1 to 17-N, are clocked-off of Rx side or drop clock signal 13, and thus operation of pointer processors 15-1 to 15-N, and more particularly buffers 17-1 to 17-N, is sychronized to drop clock signal 13. As one or more of Rx line clock signals 12-1 to 12-N may be out-of-phase, differ in frequency or differ in tolerance from drop clock signal 13, an asynchronicity may occur with respect to Rx parallel clock signals 24-1 to 24-N and drop clock signal 13. Thus, data from data output signals 25-1 to 25-N may not properly coincide with data corresponding pointer output signals 14-1 to 14-N as output from pointer processors 15-1 to 15-N, respectively, owing to misalignment with clock signal edges. Moreover, a separate pointer processor is used for each channel. Though FIG. 1 is illustratively shown for the receive side, a similiar asynchronicity problem heretofore exists on the transmit side (not shown) of network element 10.
Accordingly, it would be desirable to provide a method and apparatus that facilitates a reduction in the number of pointer processors.